Arteris Expands Multi-Die Portfolio With FlexGen

• Arteris, Inc. announced an expansion of its multi-die portfolio, including a new FlexGen Multi-Die product.
• FlexGen Multi-Die targets non-coherent AI and high-performance computing architectures.
• Ncore Multi-Die targets cache-coherent compute architectures.
• The FlexGen Multi-Die NoC IP supports bidirectional transactions over a single UCIe PHY.
• The expanded multi-die solution is available today to early access partners and strategic customers.

Portfolio Expansion

Arteris, Inc. announced an expansion of its multi-die portfolio, including a new FlexGen Multi-Die product, on September 15, 2026. The Nasdaq-listed company is headquartered in Campbell, Calif..

Product Targets

FlexGen Multi-Die targets non-coherent AI and high-performance computing architectures. It supports virtual channel link technology. The FlexGen Multi-Die NoC IP supports bidirectional transactions over a single UCIe PHY. Ncore Multi-Die targets cache-coherent compute architectures.

Interoperability Validation

Synopsys said it completed successful validation of interoperability between its silicon-proven UCIe IP and Arteris' Ncore Cache Coherent NoC IP for multi-die designs. Neeraj Paliwal is senior vice president of product management at Synopsys.

UniVista said it is working with Arteris to validate interoperability between its UCIe IP and Arteris Ncore Multi-Die. Mao Liu is vice president at UniVista.

Silitronics said it plans to leverage Arteris FlexGen technology in developing an OCP-derived chiplet architecture. Suresh Subramaniam is CTO, systems and advanced packaging at Silitronics.

Socionext is collaborating with Arteris on its UCIe-based multi-die solution, according to Daisuke Murakami. Murakami is executive chief engineer, Global Leading Group at Socionext.

Arteris' continued expansion of its multi-die portfolio supports the flexibility and productivity required for AMD's next generation of data center, client, gaming, and embedded compute products.

— Jason Miller, senior director, Silicon Design at AMD

Executive Statements

Multi-die architectures represent one of the most important changes in semiconductor design since the introduction of the SoC itself.

— K. Charles Janac, president and CEO of Arteris

Combining Cadence Physical AI platform, IP, and security solutions with Arteris' NoC IP enables accelerated silicon realization and trusted system deployment.

— David Glasco, vice president of R&D, Silicon Solutions Group at Cadence

Availability

The expanded multi-die solution is available today to early access partners and strategic customers. Magillem integration automation automates IP packaging, chiplet and multi-die integration, and hardware/software integration.

Cycuity hardware security assurance identifies vulnerabilities and verifies security requirements in multi-die systems. It is not available in all markets.